FIG. 9 illustrates a conventional chopper-type voltage comparator which is disclosed in N. Fukushima et al., "A CMOS 40 MHz 8b 105 mW Two-Step ADC", IEEE International Solid-State Circuits Conference, pp. 14-15, (1989). As shown in the figure, the conventional voltage comparator comprises an input voltage terminal 51, a reference voltage terminal 52, first to fourth switches 53, 54, 57, and 60, first and second capacitors 55 and 58, first and second inverters 56 and 59, and an output terminal 61.
The reference voltage terminal 52 inputs a reference voltage V.sub.ref, and the voltage input terminal 51 inputs an input voltage V.sub.in to be compared with the reference voltage V.sub.ref. A first terminal of the first switch 53 is connected to the input voltage terminal 51, and a first terminal of the second switch 54 is connected to the reference voltage terminal 52. A first terminal of the first capacitor 55 is connected to a second terminal of the first switch 53 and a second terminal of the second switch 54.
The input terminal of the first inverter 56 is connected to a second terminal of the first capacitor 55, and the output terminal of the inverter 56 is connected to a first terminal of the second capacitor 58. A first terminal of the third switch 57 is connected to the input terminal of the first inverter 56, and a second terminal of the switch 57 is connected to the output terminal of the inverter 56.
The input terminal of the second inverter 59 is connected to a second terminal of the second capacitor 58, and the output terminal of the inverter 59 is connected to the output terminal 61. A first terminal of the fourth switch 60 is connected to the input terminal of the second inverter 59, and a second terminal of the switch 60 is connected to the output terminal of the inverter 59.
Also, although not shown in the figure, the switches 53, 54, 57, and 60 are selectively turned ON (i.e. closed/rendered conductive) and turned OFF (i.e. opened/rendered non-conductive) via first and second drive signals P1 and P2. Specifically, when the first drive signal P1 is a logic "1", the first, third, and fourth switches 53, 57 and 60 are turned ON, and when the first drive signal PI is a logic "0", the switches 53, 57 and 60 are turned OFF. On the other hand, the second switch 54 is turned ON when the second drive signal P2 is a logic "1" and is turned OFF when the second drive signal P2 is a logic "0".
The comparing operation performed by the conventional chopper-type voltage comparator will be described with reference to FIG. 10. As shown in the figure, the voltage comparator operates in three stages. The first stage is defined when the first drive signal P1 equals "1" and the second drive signal P2 equals "0". The second stage is defined when the first drive signal P1 equals "0" and the second drive signal P2 equals "1". Finally, the third stage is defined when the first drive signal P1 again equals "1" and the second drive signal P2 again equals "0".
During the first stage (i.e. P1=1 and P2=0), the first, third, and fourth switches 53, 57, and 60 are closed, and the second switch 54 is opened. Thus, the input voltage V.sub.in is sampled and supplied to the first capacitor 55. Also, the third switch 57 connects the input and output terminals of the first inverter 56 so that the potential at the output terminal of the inverter 56 is held at a threshold voltage V.sub.LT of the inverter 56. Similarly, the fourth switch 57 connects the input and output terminals of the second inverter 59 so that the potential at the output terminal of the inverter 59 is held at the threshold voltage V.sub.LT of the inverter 59. In addition, the threshold voltages V.sub.LT of the inverters 56 and 59 are equal.
Therefore, as shown during the first stage in FIG. 10, the voltage at the first terminal of the first capacitor (i.e. at point 1) rises to the level of the input voltage V.sub.in. Also, the voltages at the input terminal of the inverter 56 (i.e. at point 2) and at the output terminal of the inverter 56 (i.e. at point 3) both equal the threshold voltage V.sub.LT. Similarly, the voltages at the input terminal of the inverter 59 (i.e. at point 4) and at the output terminal of the inverter 59 (i.e. at point 5) both equal the threshold voltage V.sub.LT.
Then, during the second stage (i.e. P1=0 and P2=1), the second switch 54 is closed, and the first, third, and fourth switches 53, 57, and 60 are opened. As a result, the reference voltage V.sub.ref is applied to the first terminal of the first capacitor 55. At this moment, the voltage at the second terminal of the capacitor 55 (i.e. the voltage at the input terminal of the first inverter 56) changes from the threshold voltage V.sub.LT by an amount which equals the difference between the input voltage V.sub.in and the reference voltage V.sub.ref (i.e. changes by an amount (V.sub.in -V.sub.ref)) In other words, the voltage at the input terminal of the inverter 56 equals V.sub.LT -(V.sub.in -V.sub.ref). As a result, the inverter 56 outputs a voltage V.sub.LT +A(V.sub.in -V.sub.ref) via its output terminal. Specifically, the inverter 56 inputs the voltage V.sub.LT -(V.sub.in -V.sub.ref) from the first capacitor 55, subtracts its threshold voltage V.sub.LT from the voltage V.sub.LT -(V.sub.in -V.sub.ref) to obtain the voltage-(V.sub.in -V.sub.ref), and amplifies the voltage -(V.sub.in -V.sub.ref) by an amplification factor -A to obtain the voltage A(V.sub.in -V.sub.ref). Then, before the voltage A(V.sub.in -V.sub.ref) is output from the inverter 56, it is added to the threshold voltage V.sub.LT of the inverter 56 to obtain the voltage V.sub.LT +A(V.sub.in -V.sub.ref). As a result, the voltage V.sub.LT +A(V.sub.in -V.sub.ref) is present at the output terminal of the inverter 56 (i.e. at the point 3).
The voltage V.sub.LT +A(V.sub.in -V.sub.ref) output from the first inverter 56 is applied via the second capacitor 58 to the input terminal of the second inverter 59 (i.e. applied to point 4). As a result, the inverter 59 outputs a voltage V.sub.LT -A.sup.2 (V.sub.in -V.sub.ref) via its output terminal. Specifically, the inverter 59 inputs the voltage V.sub.LT +A(V.sub.in-V.sub.ref) from the second capacitor 58, subtracts its threshold voltage V.sub.LT from the voltage V.sub.LT +A(V.sub.in -V.sub.ref) to obtain the voltage A(V.sub.in -V.sub.ref), and amplifies the voltage A(V.sub.in -V.sub.ref) by an amplification factor -A to obtain the voltage -A.sup.2 (V.sub.in -V.sub.ref). Then, before the voltage -A.sup.2 (V.sub.in -V.sub.ref) is output from the inverter 59, it is added to the threshold voltage V.sub.LT of the inverter 59 to obtain the voltage V.sub.LT -A.sup.2 (V.sub.in -V.sub.ref). As a result, the voltage V.sub.LT A.sup.2 (V.sub.in -V.sub.ref) is present at the output terminal of the inverter 59 (i.e. at point 5).
As illustrated above, the conventional chopper-type voltage comparator samples both the input voltage V.sub.in and the reference voltage V.sub.ref with the same capacitor 55 and adjusts the charge in the capacitor 55 based on the difference between the voltages V.sub.in and V.sub.ref. Then, the voltage difference (V.sub.in -V.sub.ref) is amplified to a desired logic level in multiple stages by the inverters 56 and 57 to obtain a voltage comparison result (i.e. the voltage output from the output terminal 61).
The conventional chopper-type voltage comparator suffers from several problems. For example, although not illustrated in FIG. 9 for the sake of clarity, the conventional voltage comparator must have many more than two stages of inverters to obtain a voltage comparison result that has a high precision and/or a desired logic level. However, using many stages of inverters substantially increases the amount of current consumed by the comparator and the size of the comparator.
Also, the conventional voltage comparator will generate an erroneous voltage comparison result if the threshold voltage in one of the inverters changes as a result of common-mode noise such as power supply noise. In other words, the inverters are connected to a power supply, and any noise contained in the power supplied to the inverters will change their threshold voltages. Similar noises may also result from noise in the ground voltage. For instance, as shown in FIG. 11, a common-mode noise may be caused when a transition is made from a state in which the first drive signal P1 equals "1" and the second drive signal P2 equals "0" to a state in which the first drive signal P1 equals "0" and the second drive signal P2 equals "1". Such noise may change the threshold voltage of the inverter 56 and create an erroneous voltage comparison result if the change is larger than the difference between the input voltage V.sub.in and the reference voltage V.sub.ref. In such case, a voltage comparison result, which is opposite to the correct voltage comparison result, is obtained. Thus, the incorrect relationship between the input voltage V.sub.in and the reference voltage V.sub.ref is indicated.
As shown in the second stage of the figure, the voltage of the noise V.sub.NOISE increases the voltage at the input terminal of the inverter 56 (i.e. at point 2) to a voltage V.sub.LT +(V.sub.NOISE -(V.sub.in -V.sub.ref) instead of the current voltage V.sub.LT -(V.sub.in -V.sub.ref). Thus, if the voltage V.sub.NOISE is greater than the voltage (V.sub.in -V.sub.ref), the voltage input to the inverter 56 will be greater than the threshold voltage V.sub.LT instead of being less than the threshold voltage V.sub.LT (see FIG. 10). As a result, the voltage V.sub.LT +A.sup.2 (V.sub.NOISE -(V.sub.in -V.sub.ref)) at the output terminal (i.e. at point 5) will be greater than the threshold voltage V.sub.LT instead of less than such voltage V.sub.LT (see FIG. 10). Thus, the voltage comparison result is incorrect.